Category

LSI Design and Verification Tools、EDA Tools

FPGA/PLD、Co-verification tools、System House Design/Construction,System Integration

Exhibit Highlights

FPGAs are now featuring 9 million system logic cells, if you stay with the conventional design and verification flow, while high quality device is demanded at low cost with short time to market, together this will absolutely rise a concern about a significant labor shortage. At the PALTEK booth, we will introduce the latest technology and tools to address this serious problem.

- Bit accurate C++ based design, verification, high level synthesis and equivalency checking
- Application of Formal technology to identify functional bugs even before simulation gets started
- AI based fully automated FPGA optimization and process exploration technology
- FPGA development on the Cloud
- FPGA Industry standard simulator : ModelSim / QuestaSim

We are looking forward to welcome you to our booth and to serve your needs.

Applicable field

• Automotive
• Consumer electronics / AV / Amusement
• FA
• New communication / Mobile / Network
• Smart Energy
• Social Infrastructure
• Medical / Nursing care
• Logistics
• Agriculture / Fisheries / Mining
• Aerospace
• Finance (bank / securities / insurance)

Contact

*The following information is provided to enable inquiries to exhibitors.
Unauthorized use and reproduction for any other purpose is prohibited.

PALTEK Design Service Division 6F, Square Building, 2-3-12, ShinYokohama, Kouhoku-ku, Yokohama-shi, JAPAN

TEL : 045-477-2009 FAX : 045-477-2146 E-mail : info_pal@paltek.co.jp URL : https://www.paltek.co.jp