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Event Organizer Japan Embedded Systems Technology Association(JASA)
Event ManagerICS Convention Design Inc.
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Conference Program
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FPGA Track
| FP-1 | 11.17 [thu] 10:00-10:45 Annex Hall[F202] | ||
| No Need to Fear FPGA! Introduction to FPGA Design which you can start right now | ||
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| FP-2 | 11.17 [thu] 11:00-11:45 Annex Hall[F202] | ||
| Make full use of the ChipScope Pro XILINX debug tool | ||
| - Aren't you wasting time without knowing about it? - | ||
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| FP-3 | 11.17 [thu] 12:00-12:45 Annex Hall[F202] | ||
| Importance of FPGA functional verification due to difficulty of debugging | ||
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| FP-4 | 11.17 [thu] 13:00-13:45 Annex Hall[F202] | ||
| Introduction of the Altera 28nm FPGA product portfolio | ||
| - 45-minute guide to the leading-edge 28nm FPGA technology - | ||
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| FP-5 | 11.17 [thu] 14:00-14:45 Annex Hall[F202] | ||
| Industry first! FPGA and Tools that fully support floating-point math.h functions | ||
| - Explanation and demonstration of devices and tools supporting floating point - | ||
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| FP-6 | 11.17 [thu] 15:00-15:45 Annex Hall[F202] | ||
| Detailed case studies of solutions using innovative FPGA as the next-generation SOC devices | ||
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| FP-7 | 11.17 [thu] 16:00-16:45 Annex Hall[F202] | ||
| FullHD Video Image Processing: Reducing development time from 6 months to 1 week | ||
| - Make better use of FPGA! - | ||
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| FP-8 | 11.18 [fri] 10:00-10:45 Annex Hall[F202] | ||
| Up-to-date information: Implement with FPGA by Altera! Optimal embedded processor system | ||
| - Update! Introduction of an extensive processor architecture portfolio - | ||
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| FP-9 | 11.18 [fri] 11:00-11:45 Annex Hall[F202] | ||||
| FPGA-based high speed interface solutions | ||||
| - Introduction of FPGA-based V-by-One® HS and USB 3.0 solutions - | ||||
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| FP-10 | 11.18 [fri] 12:00-12:45 Annex Hall[F202] | ||
| PSoC Can do what CPLD Can't | ||
| - Add an MCU and rich analog features to your CPLD - | ||
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| FP-11 | 11.18 [fri] 13:00-13:45 Annex Hall[F202] | ||
| "All In" - Trend of Next Era Programmable Logic | ||
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| FP-12 | 11.18 [fri] 14:00-14:45 Annex Hall[F202] | ||
| FPGA Case Study: EIZO "Super- Resolution" Monitors | ||
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| FP-13 | 11.18 [fri] 15:00-15:45 Annex Hall[F202] | ||
| Interfacing 1866Mbps DDR3 SDRAM with Xilinx 28nm FPGA | ||
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